View ICS9LP525-2_5061332.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DATASHEET
56-pin CK505 for Intel Desktop Systems
Recommended Application: CK505 clock, 56-pin Intel Yellow Cover part Output Features: * 2 - CPU differential low power push-pull pairs * 7- SRC differential low power push-pull pairs * 1 - CPU/SRC selectable differential low power push-pull pair * 1 - SRC/DOT selectable differential low power push-pull pair * 5 - PCI, 33MHz * 1 - PCI_F, 33MHz free running * 1 - USB, 48MHz * 1 - REF, 14.318MHz Key Specifications: * CPU outputs cycle-cycle jitter < 85ps * SRC output cycle-cycle jitter < 125ps * PCI outputs cycle-cycle jitter < 250ps * +/- 100ppm frequency accuracy on all outputs * SRC are PCIe Gen2 compliant
ICS9LP525-2
Features/Benefits: * Supports spread spectrum modulation, default is 0.5% down spread * Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning * Selectable SRC differential push-pull pair/two single ended outputs Table 1: CPU Frequency Select Table
FSLC B0b7 0 0 0 0 1 1 1 1
2
FSLB B0b6 0 0 1 1 0 0 1 1
1
FSLA B0b5 0 1 0 1 0 1 0 1
1
CPU MHz 266.66 133.33 200.00 166.66 333.33 100.00 400.00
SRC MHz
PCI MHz
REF MHz
USB DOT MHz MHz
100.00
33.33 14.318 48.00 96.00
Reserved
1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. 2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values.
Pin Configuration
PCI0/CR#_A 1 VDDPCI 2 PCI1/CR#_B PCI2/TME PCI3/CFG0 PCI4/SRC5_EN PCI_F5/ITP_EN GNDPCI VDD48 USB_48MHz/FSLA GND48 VDD96_IO DOTT_96/SRCT0 DOTC_96/SRCC0 GND VDD SRCT1/SE1 SRCC1/SE2 GND VDDPLL3_IO SRCT2/SATAT SRCC2/SATAC GNDSRC SRCT3/CR#_C SRCC3/CR#_D VDDSRC_IO SRCT4 SRCC4 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 SCLK 55 SDATA 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 REF0/FSLC/TEST_SEL VDDREF X1 X2 GNDREF FSLB/TEST_MODE CK_PWRGD/PD# VDDCPU CPUT0 CPUC0 GNDCPU CPUT1_F CPUC1_F VDDCPU_IO VOUT CPUT2_ITP/SRCT8 CPUC2_ITP/SRCC8 VDDSRC_IO SRCT7/CR#_F SRCC7/CR#_E GNDSRC SRCT6 SRCC6 VDDSRC PCI_STOP#/SRCT5 CPU_STOP#/SRCC5
56-SSOP & TSSOP
IDT(R) PC MAIN CLOCK 1397--11/08/10
9LP525-2
1
ICS9LP525-2 PC MAIN CLOCK
Pin Description
PIN # PIN NAME TYPE DESCRIPTION
3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair The power-up default is PCI0 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 0 of SMBus address space . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CRA#_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 7 0 = PCI0 enabled (default) 1= CRA# enabled. Byte 5, bit 6 controls whether CRA# controls SRC0 or SRC2 pair Byte 5, bit 6 0 = CRA# controls SRC0 pair (default), 1= CRA# controls SRC2 pair Power supply for PCI clocks, nominal 3.3V 3.3V PCI clock output/Clock Request control B for either SRC1 or SRC4 pair The power-up default is PCI1 output, but this pin may also be used as a Clock Request control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 1 of SMBus address space . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CRB#_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 5 0 = PCI1 enabled (default) 1= CRB# enabled. Byte 5, bit 6 controls whether CRB# controls SRC1 or SRC4 pair Byte 5, bit 4 0 = CRB# controls SRC1 pair (default) 1= CRB# controls SRC4 pair 3.3V PCI clock output / Trusted Mode Enable(TME) Latched Input. This pin is sampled on power-up as follows 0=Overclocking of CPU and SRC allowed 1=Overclocking of CPU and SRC NOT allowed After being sampled on power-up, this pin becomes a 3.3V PCI Output 3.3V PCI clock output/Configuration Strap. See PCI3 Configuration Table for more information 3.3V PCI clock output / SRC5 pair or PCI_STOP#/CPU_STOP# enable strap. On powerup, the logic value on this pin determines if the SRC5 pair is enabled or if CPU_STOP#/PCI_STOP# is enabled (pins 29 and 30). The latched value controls the pin function on pins 29 and 30 as follows 0 = PCI_STOP#/CPU_STOP# 1 = SRC5/SRC5# Free running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the state of the PCI_STOP# pin. On powerup, the state of this pin determines whether pins 38 and 39 are an ITP or SRC pair. 0 =SRC8/SRC8# 1 = ITP/ITP# Ground pin for the PCI outputs Power pin for the 48MHz output and PLL.3.3V 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. / Fixed 48MHz USB clock output. 3.3V. Ground pin for the 48MHz outputs Power supply for DOT96 clocks, nominal 0.8V from source/emitter of external pass transistor. True clock of low power differential SRC or DOT96. The power-up default function is SRC0. After powerup, this pin function may be changed to DOT96 via SMBus Byte 1, bit 7 as follows: 0= SRC0 1=DOT96 Complement clock of low power differential SRC or DOT96. The power-up default function is SRC0#. After powerup, this pin function may be changed to DOT96# via SMBus Byte 1, bit 7 as follows 0= SRC0# 1=DOT96# Ground pin. Power supply, nominal 3.3V True clock of low power differential SRC1 clock pair / 3.3V single-ended output. The powerup default is 100 MHz SRC, -0.5% downspread. The pin function may be changed via SMBus B1b[4:1] Complement clock of push-pull differential SRC1 clock pair / 3.3V single-ended output. The powerup default is 100 MHz SRC, 0.5% downspread. The pin function may be changed via SMBus B1b[4:1] Ground pin. Power supply for PLL3. 0.8V nominal from source/emitter of external pass transistor True clock of low power differentiall SRC/SATA clock pair. Complement clock of differential push-pull SRC/SATA clock pair. Ground pin for the SRC outputs
1
PCI0/CR#_A
I/O
2
VDDPCI
PWR
3
PCI1/CR#_B
I/O
4 5
PCI2/TME PCI3/CFG0
I/O I/O
6
PCI4/SRC5_EN
I/O
7 8 9 10 11 12 13
PCI_F5/ITP_EN GNDPCI VDD48 USB_48MHz/FSLA GND48 VDD96_IO DOTT_96/SRCT0
I/O PWR PWR I/O PWR PWR OUT
14 15 16 17 18 19 20 21 22 23
DOTC_96/SRCC0 GND VDD SRCT1/SE1 SRCC1/SE2 GND VDDPLL3_IO SRCT2/SATAT SRCC2/SATAC GNDSRC
OUT PWR PWR OUT OUT PWR PWR OUT OUT PWR
IDTTM/ICSTM PC MAIN CLOCK
1397--11/08/10
2
ICS9LP525-2 PC MAIN CLOCK
Pin Description (continued)
PIN # PIN N A ME TYPE D ESC R IPTION
Complementary cloc k of differential SRC clock pair/ Clock Reques t control D for either SRC1 or SRC4 pair The power-up default is SRCCLK3 output, but this pin may als o be used as a Clock Request control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Cloc k Request Pin, the SRC output must first be disabled in byte 4, bit 7 of SMBus addres s s pace . After the SRC output is disabled, the pin c an then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CRD#_EN bit located in byte 5 of SMBUs address space. By te 5, bit 1 0 = SRC3 enabled (default) 1= CRD# enabled. By te 5, bit 0 controls whether CRD# controls SRC1 or SRC4 pair Byte 5, bit 0 0 = CRD# controls SRC1 pair (default), 1= CRD# c ontrols SRC4 pair Power supply for SRC clocks. 0.8V nominal from source/emitter of external pass transis tor True clock of low power differential SRC cloc k pair. Complement clock of low power differential SRC clock pair. Ref, XTAL power supply, nominal 3.3V Stops all PCICLKs at logic 0 level, when low. F ree running PCICLKs are not effected by this input. / T rue clock of differential pushpull SRC pair. Supply for SRC PLL, 3.3V nominal Complement clock of low power differential SRC clock pair. True clock of low power differential SRC cloc k pair. G round pin for the SRC outputs Complement clock of differential push-pull SRC clock pair. / Clock Request c ontrol E for SRC6 pair. T he power-up default is SRC7#, but this pin may also be used as a Clock Reques t control of SRC6 v ia SMBus . Before configuring this pin as a Clock Request Pin, the SRC7 output pair must first be disabled in byte 3, bit 3 of SMBus configuration space . After the SRC output is disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC6 pair using byte 6, bit 7 of SMBus configuration space By te 6, bit 7 0 = SRC7# enabled (default) 1= CRE# enabled. True clock of differential push-pull SRC cloc k pair/ Clock Reques t control 8 for SRC8 pair The power-up default is SRC7, but this pin may also be used as a Clock Request control of SRC8 via SMBus. Before c onfiguring this pin as a Clock Request Pin, the SRC7 output pair must first be disabled in by te 3, bit 3 of SMBus configuration s pace After the SRC output is disabled (high-Z), the pin can then be set to serve as a Cloc k Request for SRC8 pair using by te 6, bit 6 of SMBus configuration space. By te 6, bit 6 0 = SRC7# enabled (default) 1 = CRF# enabled. Power supply for SRC clocks. 0.8V nominal from source/emitter of external pass transis tor Complement clock of low power differential CPU2/Complement clock of differential SRC pair. The function of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. T he function is as follows: Pin 7 latc hed input Value 0 = SRC8# 1 = ITP# True clock of low power differential CPU2/True clock of differential SRC pair. The function of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. T he function is as follows: Pin 7 latc hed input Value 0 = SRC8 1 = ITP O P Amp comparator output. T his pin drives the base/gate of the ex ternal pass trans istor Supply for CPU clocks . 0.8V nominal from s ource/emitter of external pass trans istor Complementary cloc k of low power differential pus h-pull CPU output. This CPU clock is free running during iAMT. True clock of differential push-pull CPU cloc k pair. T his clock is free running during iAMT. G round pin for the CPU outputs Complement clock of low power differential CPU clock pair. True clock of low power differential CPU cloc k pair. Supply for CPU PLL, 3.3V nominal Notifies CK505 to sample latched inputs , or iAMT entry/exit, or PWRDWN# mode 3.3V tolerant input for CPU frequency selection. Refer to input elec tric al characteristic s for Vil_FS and Vih_F S values. TEST_MO DE is a real time input to select between Hi-Z and REF /N divider mode while in test mode. Refer to Test Clarification Table. G round pin for the REF outputs. Cry stal output, Nominally 14.318MHz Cry stal input, Nominally 14.318MHz. Ref, XTAL power supply, nominal 3.3V 14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency selection. Refer to input electrical charac teristics for Vil_F S and Vih_F S values. /TEST_Sel: 3-level latc hed input to enable test mode. Refer to Tes t Clarification T able Data pin for SMBus circ uitry , 5V tolerant. Clock pin of SMBus circuitry, 5V tolerant.
25
SRCC3/CR#_D
I/O
26 27 28 29 30 31 32 33 34
VDDSRC_IO SRCT4 SRCC4 CPU_ST O P#/SRCC5 PCI_ST O P#/SRCT 5 VDDSRC SRCC6 SRCT6 G NDSRC
PWR O UT O UT I/O I/O PWR O UT O UT PWR
35
SRCC7/CR#_E
I/O
36
SRCT7/CR#_F
I/O
37
VDDSRC_IO
PWR
38
CPUC2_IT P/SRCC8
O UT
39
CPUT2_IT P/SRCT8
O UT
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
VO UT VDDCPU_IO CPUC1_F CPUT1_F G NDCPU CPUC0 CPUT0 VDDCPU CK_PWRG D/PD# F SLB/T EST _MO DE G NDREF X2 X1 VDDREF REF 0/F SLC/TEST_SEL SDATA SCLK
PWR PWR O UT O UT PWR O UT O UT PWR IN IN PWR O UT IN PWR I/O I/O IN
IDTTM/ICSTM PC MAIN CLOCK
1397--11/08/10
3
ICS9LP525-2 PC MAIN CLOCK
General Description
ICS9LP525-2 is compliant Intel CK505 Yellow Cover specification. This clock synthesizer provides a single chip solution for Intel desktop chipsets. ICS9LP525-2 is driven with a 14.318MHz crystal. It also provides a tight ppm accuracy output for Serial ATA and PCI-Express support.
Block Diagram
X1 X2 REF REF CPU(1:0)
OSC
SRC8/ITP
CPU
CPU PLL1 SS
SRC
SRC_MAIN
SRC(7:3)
PCI33MHz SRC PCI(5:0) PCI33MHz
PLL3 SS
SRC2/SATA FSLA CKPWRGD/PD# PCI_STOP# CPU_STOP# CR#_(A:F) SRC5_EN ITP_EN FSLC/TESTSEL FSLB/TESTMODE SRC1/SE(2:1)
Control Logic
Differential Output
SE Outputs
7
SATA
SRC0/DOT96
PLL2 Non-SS
DOT96MHz 48MHz 48MHz
Power Groups
Pin Number VDD GND 41, 47 44 16 15 26, 31, 37 20 12 9 53 2 23, 34 19 11 11 50 8 Description CPUCLK Master Clock, Analog SRCCLK PLL3/SE DOT 96Mhz USB 48 Xtal, REF PCICLK
IDTTM/ICSTM PC MAIN CLOCK
1397--11/08/10
4
ICS9LP525-2 PC MAIN CLOCK
External Pass Transistor Connection for Desktop Applications
ICS9LP525-2
VDDCPU_IO, Pin 41
3.3V
R=15 3.3V
CPU_IO Decoupling Network
+ Vref
VOUT PIN 40
2N3904 R=33
96_IO Decoupling Network
C=100pF
VD D _IO 0. 8V N OM .
C >= 40uF
PLL3_IO Decoupling Network
SRC_IO Decoupling Network
VDDSRC_IO Pin 37, 26
VDDPLL3_IO, Pin 20
VDD96_IO, Pin 12
IDTTM/ICSTM PC MAIN CLOCK
1397--11/08/10
5
ICS9LP525-2 PC MAIN CLOCK
A b so lu te Maxim u m R atin g s - D C P aram eters
P A RA M E TE R M ax im um S upply V oltage M ax im um S upply V oltage M ax im um Input V oltage M inim um Input V oltage Cas e Tem perature S torage Tem perature Input E S D protec tion
1 G uaranteed 2
SYM BOL V DDx x x V DDx x x _IO V IH V IL Tc as e Ts E S D prot
CO NDITIO NS S upply V oltage Low-V oltage Differential I/O S upply 3.3V Inputs A ny Input Hum an B ody M odel
M IN
MAX 4.6 3.8 4.6 115 150
G ND - 0.5 -65 2000
UNITS V V V V

Notes 7 7 4,5,7 4,7 4,7 6,7
C C V
by des ign and c harac teriz ation, not 100% tes ted in produc tion.
O peration under thes e c onditions is neither im plied, nor guaranteed.
Electrical Characteristics - Input/Supply/Common Output DC Parameters
PARAMETER Ambient Operating Temp Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Low Threshold InputHigh Voltage Low Threshold InputFSC = '1' Voltage Low Threshold InputFSA,FSB = '1' Voltage Low Threshold InputLow Voltage PCI3/CFG0 Input PCI3/CFG0 Input PCI3/CFG0 Input Input Leakage Current Input Leakage Current Output High Voltage Output Low Voltage Operating Supply Current iAMT Mode Current Powerdown Current Input Frequency Pin Inductance Input Capacitance SYMBOL Tambient VDDxxx VDDxxx_IO VIHSE VILSE VIH_FS_TEST VIH_FS_FSC VIH_FS_FSAB VIL_FS VIL_CFGHI VIL_CFGMID VIL_CFGLO I IN I INRES VOHSE VOLSE IDDOP3.3 IDDOPIO IDDiAMT3.3 IDDiAMTIO IDDPD3.3 IDDPDIO Fi Lpin CIN COUT CINX TSTAB TDRCROFF TDRCRON TDRSRC TFALL TRISE VDD VOLSMB IPULLUP TRI2C TFI2C FSMBUS fSSMOD Triangular Modulation 30 CONDITIONS Supply Voltage Low-Voltage Differential I/O Supply Single-ended 3.3V inputs Single-ended 3.3V inputs 3.3 V +/-5% 3.3 V +/-5% 3.3 V +/-5% 3.3 V +/-5% Optional input, 2.75V typ. Optional input, 1.65V typ. Optional input, 0.55V typ. VIN = VDD , VIN = GND Inputs with pull up or pull down resistors VIN = VDD , VIN = GND Single-ended outputs, IOH = -1mA Single-ended outputs, IOL = 1 mA Full Active, CL = Full load; Idd 3.3V Full Active, CL = Full load; IDD IO M1 mode, 3.3V Rail M1 Mode, IO Rail Power down mode, 3.3V Rail Power down mode, IO Rail VDD = 3.3 V Logic Inputs Output pin capacitance X1 & X2 pins From VDD Power-Up or de-assertion of PD to 1st clock Output stop after CR deasserted Output run after CR asserted CPU output enable after PCI_STOP# de-assertion Fall/rise time of all 3.3V control inputs from 20-80% 2.7 @ IPULLUP SMB Data Pin (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15) 4 1000 300 100 33 MIN 0 3.135 0.72 2 VSS - 0.3 2 0.7 0.7 VSS - 0.3 2.4 1.3 VSS - 0.3 -5 -200 2.4 0.4 200 70 80 10 5 0.1 15 7 5 6 6 1.8 400 0 10 10 10 5.5 0.4 MAX 70 3.465 0.9 VDD + 0.3 0.8 VDD + 0.3 1.5 VDD+0.3 0.35 VDD+0.3 2 0.9 5 200 UNITS C V V V V V V V V V V V uA uA V V mA mA mA mA mA mA MHz nH pF pF pF ms ns us ns ns ns V V mA ns ns kHz kHz 1 1 10 9 9 9 2 Notes
10 3 3 8 8
10
1.5
Clk Stabilization Tdrive_CR_off Tdrive_CR_on Tdrive_CPU Tfall_SE Trise_SE SMBus Voltage Low-level Output Voltage Current sinking at VOLSMB = 0.4 V SCLK/SDATA Clock/Data Rise Time SCLK/SDATA Clock/Data Fall Time Maximum SMBus Operating Frequency Spread Spectrum Modulation Frequency
IDTTM/ICSTM PC MAIN CLOCK
1397--11/08/10
6
ICS9LP525-2 PC MAIN CLOCK
NOTES on DC Parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
1 2 3 4 5 6 7 8 9
Signal is required to be monotonic in this region. input leakage current does not include inputs with pull-up or pull-down resistors 3.3V referenced inputs are: PCI_STOP#, CPU_STOP#, TME, SRC5_EN, ITP_EN, SCLKL, SDATA, TESTMODE, TESTSEL, CKPWRGD and CR# inputs if selected. Intentionally blank Maximum VIH is not to exceed VDD Human Body Model Operation under these conditions is neither implied, nor guaranteed. Frequency Select pins which have tri-level input PCI3/CFG0 is optional If present. Not all parts have this feature.
10
AC Electrical Characteristics - Low Power Differential Outputs
PARAMETER Rising Edge Slew Rate Falling Edge Slew Rate Slew Rate Variation Differential Voltage Swing Crossing Point Voltage Crossing Point Variation Maximum Output Voltage Minimum Output Voltage Duty Cycle CPU Skew CPU[1:0] Skew CPU[2_ITP:0] Skew SRC[10:0] Skew SYMBOL tSLR tFLR tSLVAR VSWING VXABS VXABSVAR VHIGH VLOW DCYC CPUSKEW CPUSKEW10 CPUSKEW20 SRCSKEW CONDITIONS Averaging on Averaging on Averaging on Averaging off Averaging off Averaging off Averaging off Averaging off Averaging on Averaging on Differential Measurement Differential Measurement Differential Measurement MIN 2.5 2.5 300 300 MAX 4 4 20 550 140 1150 55 100 100 150 3000 UNITS NOTES V/ns V/ns % mV mV mV mV mV % ps ps ps ps 2, 3 2, 3 1, 10 2 1,4,5 1,4,9 1,7 1,8 2 1 1 1,6,11
-300 45
NOTES on DIF Output AC Specs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
1 2 3 4
Measurement taken for single ended waveform on a component test board (not in system) Measurement taken from differential waveform on a component test board. (not in system) Slew rate emastured through V_swing voltage range centered about differential zero
Vcross is defined at the voltage where Clock = Clock#, measured on a component test board (not in system) 5 Only applies to the differential rising edge (Clock rising, Clock# falling)
6 7 8 9
Total distributed intentional SRC to SRC skew. PCIE Gen2 outputs (SRC3, 4, 6 and 7) will have 0 nominal skew. Maximum allowable interpair skew is 150 ps. The max voltage including overshoot. The min voltage including undershoot.
The total variation of all Vcross measurements in any particular system. Note this is a subset of V_cross min/mas (V_Cross absolute) allowed. The intent is to limit Vcross induced modulation by setting C_cross_delta to be smaller than V_Cross absolute.
10
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations.
11
For PCIe Gen2 compliant devices, SRC 3, 4, 6, and 7 will have 0 ps nominal skew.
C lock Jitter S pecs - Low P ower D ifferential Outputs
P A RA M E TE R CP U J itter - Cy c le to Cy c le S RC J itter - Cy c le to Cy c le DOT J itter - Cy c le to Cy c le
1
S Y M B OL CP UJ C2C S RCJ C2C DOTJ C2C
CONDITIONS Differential M eas urem ent Differential M eas urem ent Differential M eas urem ent
M IN
MAX 85 125 250
UNITS NOTE S ps ps ps 1 1,2 1
N O T ES o n D IF O u tp u t Jitter: (u n less o th erw ise n o ted , g u aran teed b y d esig n an d ch aracteriz atio n , n o t 100% tested in p ro d u ctio n ). J Itter s pec s are s pec ified as meas ured on a c loc k c harac teriz ation board. Sy s tem des igners need to tak e s pec ial c are not to us e thes e numbers , as the in-s y s tem performanc e w ill be s omew hat degraded. T he rec eiv er EMT S (c his pet or C PU ) w ill hav e the rec eiv er jitter s pec s as meas ured ina real s y s tem.
2
Phas e jitter requirement: T he deis gnated G e2 outputs w ill meet the referenc e c loc k jitter requiremernts from the PC I Ex pres s G en2 Bas e Spec . T he tes t is performed on a c omponnet tes t board under quiet c ondittions w ith all outputs on. J itter analy s is is performed us ing the s tandardiz ed tool prov ided by the PC I SIG .
IDTTM/ICSTM PC MAIN CLOCK
1397--11/08/10
7
ICS9LP525-2 PC MAIN CLOCK
Differential Clock Tolerances
PPM tolerance Cycle to Cycle Jitter Spread CPU 100 85 -0.50% SRC 100 125 -0.50% DOT96 100 250 0 BMC133 100 125 -0.50% ppm ps %
Clock Periods - Differential Outputs with Spread Spectrum Disabled
Center Freq. MHz 100.00 133.33 166.67 200.00 266.67 333.33 400.00 100.00 96.00 Measurement Window 1us 0.1s 0.1s 0.1s -SSC - ppm + ppm 0 ppm -c2c jitter Short-Term Long-Term Long-Term Period AbsPer Average Average Average Nominal Min Min Min Max 9.91400 9.99900 10.00000 10.00100 7.41425 7.49925 7.50000 7.50075 5.91440 5.99940 6.00000 6.00060 4.91450 4.99950 5.00000 5.00050 3.66462 3.74962 3.75000 3.75037 2.91470 2.99970 3.00000 3.00030 2.41475 2.49975 2.50000 2.50025 9.87400 9.99900 10.00000 10.00100 10.16563 10.41563 10.41667 10.41771 1 Clock 1us +SSC Short-Term Average Max 1 Clock +c2c jitter Units Notes AbsPer Max 10.08600 7.58575 6.08560 5.08550 3.83537 3.08530 2.58525 10.12600 10.66771 ns ns ns ns ns ns ns ns ns 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2
SSC OFF
CPU
SRC/SATA DOT96
Clock Periods - Differential Outputs with Spread Spectrum Enabled
Center Freq. MHz 99.75 133.00 166.25 199.50 266.00 332.50 399.00 99.75 Measurement Window 1us 0.1s 0.1s 0.1s -SSC - ppm + ppm 0 ppm -c2c jitter Short-Term Long-Term Long-Term Period AbsPer Average Average Average Nominal Min Min Min Max 9.91406 9.99906 10.02406 10.02506 10.02607 7.41430 7.49930 7.51805 7.51880 7.51955 5.91444 5.99944 6.01444 6.01504 6.01564 4.91453 4.99953 5.01203 5.01253 5.01303 3.66465 3.74965 3.75902 3.75940 3.75977 2.91472 2.99972 3.00722 3.00752 3.00782 2.41477 2.49977 2.50602 2.50627 2.50652 9.87406 9.99906 10.02406 10.02506 10.02607 1 Clock 1us +SSC Short-Term Average Max 10.05107 7.53830 6.03064 5.02553 3.76915 3.01532 2.51277 10.05107 1 Clock +c2c jitter Units Notes AbsPer Max 10.13607 7.62330 6.11564 5.11053 3.85415 3.10032 2.59777 10.17607 ns ns ns ns ns ns ns ns 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2
SSC ON
CPU
SRC
1 2
Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy specifications are guaranteed with the assumption that the crystal input is tuned to exactly 14.31818MHz.
IDTTM/ICSTM PC MAIN CLOCK
1397--11/08/10
8
ICS9LP525-2 PC MAIN CLOCK
E lectrical C haracteristics - P C IC LK /P C IC LK _F
P A RA M E TE R Long A c c urac y Cloc k period A bs olute m in/m ax period Ris ing E dge S lew Rate Falling E dge S lew Rate P in to P in S k ew Intential P CI to P CI delay Duty Cy c le J itter, Cy c le to c y c le S Y M B OL ppm T period T abs t SLR t FLR t s k ew t s k ew d t1 t jc y c -c y c CONDITIONS s ee Tperiod m in-m ax v alues 33.33M Hz output no s pread 33.33M Hz output s pread 33.33M Hz output no s pread 33.33M Hz output nom inal/s pread M eas ured from 0.8 to 2.0 V M eas ured from 2.0 to 0.8 V V T = 1.5 V V T = 1.5 V V T = 1.5 V V T = 1.5 V M IN -100 29.99700 30.08421 29.49700 29.56617 1 1 100 45 MAX 100 30.00300 30.23459 30.50300 30.58421 4 4 250 200 55 500 UNITS ppm ns ns ns ns V /ns V /ns ps ps % ps NOTE S 1,2 2 2 2 2 1 1 2 2 2 2
Intentional PCI Clock to Clock Delay
200 ps nominal steps
PCI0 PCI1 PCI2 PCI3 PCI4 PCI_F5
1.0ns
E lectrical C haracteristics - U S B 48MH z
P A RA M E TE R Long A c c urac y Cloc k period A bs olute m in/m ax period CLK High Tim e CLK Low tim e Ris ing E dge S lew Rate Falling E dge S lew Rate Duty Cy c le J itter, Cy c le to c y c le S Y M B OL ppm T period T abs T HIG H T LO W t SLR t FLR d t1 t jc y c -c y c CONDITIONS s ee Tperiod m in-m ax v alues 48.00M Hz output nom inal 48.00M Hz output nom inal M IN -100 20.83125 20.48125 8.216563 7.816563 1 1 45 MAX 100 20.83542 21.18542 11.15198 10.95198 2 2 55 350 UNITS ppm ns ns V V V /ns V /ns % ps NOTE S 2,4 2,3 2
M eas ured from 0.8 to 2.0 V M eas ured from 2.0 to 0.8 V V T = 1.5 V V T = 1.5 V
1 1 2 2
E lectrical C h aracteristics - R E F-14.318MH z
P A RA M E TE R Long A c c urac y Cloc k period A bs olute m in/m ax period CLK High Tim e CLK Low tim e Ris ing E dge S lew Rate Falling E dge S lew Rate Duty Cy c le J itter, Cy c le to c y c le
1 2 3 4
S Y M B OL ppm Tperiod Tabs THIG H TLO W tS LR tFLR dt1 tjc y c -c y c
CONDITIONS s ee Tperiod m in-m ax v alues 14.318M Hz output nom inal 14.318M Hz output nom inal
M eas ured from 0.8 to 2.0 V M eas ured from 2.0 to 0.8 V V T = 1.5 V V T = 1.5 V
M IN -100 69.82033 69.83400 29.97543 29.57543 1 1 45
MAX 100 69.86224 70.84800 38.46654 38.26654 4 4 55 1000
UNITS ppm ns ns V V V /ns V /ns % ps
Notes 2, 4 2, 3 2
1 1 2 2
NO T ES o n SE o u tp u ts: (u n less o th erw ise n o ted , g u aran teed b y d esig n an d ch aracteriz atio n , n o t 100% tested in p ro d u ctio n ). Edge rate in s y s tem is meas ured from 0.8V to 2.0V. Duty c y c le, Peroid and J itter are meas ured w ith res pec t to 1.5V T he av erage period ov er any 1us period of time Us ing frequenc y c ounter with the meas urment interv al equal or greater that 0.15s , target frequenc ies are 14.318180 MHz , 33.333333MHz and 48.000000MHz
IDTTM/ICSTM PC MAIN CLOCK
1397--11/08/10
9
ICS9LP525-2 PC MAIN CLOCK
Table 1: CPU Frequency Select Table FSLC B0b7 0 0 0 0 1 1 1 1
2
FS LB B0b6 0 0 1 1 0 0 1 1
1
FSLA B0b5 0 1 0 1 0 1 0 1
1
CPU MHz 266.66 133.33 200.00 166.66 333.33 100.00 400.00
SRC MHz
PCI MHz
REF MHz
USB DOT MHz MHz
100.00
33.33 14.318 48.00 96.00
Reserved
1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. 2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values.
Table 2: PLL3 Quick Configuration (only applies in Mode 0, see Table 6) Spread Pin 17 Pin 18
B1b4 B1b3 B1b2 B1b1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 MHz 100.00 100.00 100.00 100.00 100.00 100.00 N/A 24.576 24.576 98.304 27.000 25.000 N/A N/A N/A MHz 100.00 100.00 100.00 100.00 100.00 100.00 N/A 24.576 98.304 98.304 27.000 25.000 N/A N/A N/A %
Comment
PLL 3 disabled 0.5% Down Spread SRC clocks from SRC_MAIN 0.5% Down Spread Only SRCCLK1 from PLL3 1% Down Spread Only SRCCLK1 from PLL3 1.5% Down Spread Only SRCCLK1 from PLL3 2% Down Spread Only SRCCLK1 from PLL3 2.5% Down Spread Only SRCCLK1 from PLL3 N/A N/A None 24.576Mhz on SE1 and SE2 None 24.576Mhz on SE1, 98.304Mhz on SE2 None 98.304Mhz on SE1 and SE2 None 27Mhz on SE1 and SE2 None 25Mhz on SE1 and SE2 N/A N/A N/A N/A N/A N/A
Table 3: IO_Vout select table B9b2 B9b1 B9b0 IO_Vout 0 0 0 0.3V 0 0 1 0.4V 0 1 0 0.5V 0 1 1 0.6V 1 0 0 0.7V 1 0 1 0.8V 1 1 0 0.9V 1 1 1 1.0V
IDTTM/ICSTM PC MAIN CLOCK 1397--11/08/10
10
ICS9LP525-2 PC MAIN CLOCK
Table 4: Device ID table
B8b7 0 B8b6 0 B8b5 0 B8b4 0 Comment
56 pin TSSOP
Table 5: Slew Rate Selection Table Bit 1 0 0 1 1 Bit 0 0 1 0 1 Slew Rate HI-Z 0.7X (1.4V/ns) 0.8X (1.6 V/ns) 1X (2.0 V/ns)
Table 6. PCI3 Configuration Table Note: 2 bits are needed since SRC_Main_SE CFG0 is tri-level input PCI3/CFG0 PCI2/TME L PCI3_CFG1 PCI3_CFG0 HW Strap HW Strap (Byte 11, bit 7) (Byte 11, bit 6) (Byte 0, bit 2) Config Mode Low 0 or 1 0 0 0 0 = Default Mid 0 or 1 0 1 1 1 High TME=0 1 0 1 2 High TME=1 1 1 1 3 Table 7. PLL Modes for PCI3 Configurations PLL1 PLL2 Config Outputs SSC Outputs Mode
SSC
PLL3 Outputs SSC
CPU/SRC/ 0 = Default PCI Down USB NA 1 CPU Down USB NA 2 CPU Center USB NA 3 CPU Center USB/LAN25 NA *Note: In Mode 3, Byte 8, bit (1:0) must be set to '1' to enable pin 17,18
SRC/PCI SRC/PCI SRC/PCI
Down Down Down
PLL Source PLL1 (Table 2 applies) 100MHz 100MHz PLL3 100MHz PLL3 25MHz SE PLL2*
SRC1
Table 8. ME Clock Selection Table PCIF5/ ITP_EN Description iAMT_EN CPU2_AMT_EN CPU1_AMT_EN Reserved x 1 0 0 x 1 0 1 Default, CPU1 = iAMT Clock 1 1 1 0 CPU2 = iAMT Clock 1 1 1 1 CPU1 and CPU2 both run in iAMT mode
IDTTM/ICSTM PC MAIN CLOCK
1397--11/08/10
11
ICS9LP525-2 PC MAIN CLOCK
PCI_STOP# Power Management Differential Clocks (Except CPU) Stoppable Free running Stoppable Free running Running Running Running Running CK= High Running CK# = Low Low Low CK= Pull down Running CK# = Low Low CK= Pull down, CK# = Low Single-ended Clocks
SMBus OE Bit
PCI_STOP# 1 0 X
Enable
Disable
CPU_STOP# Power Management SMBus OE Bit PCI_STOP# 1 Enable 0 Disable CR# Power Management SMBus OE Bit Enable Disable PD# Power Management Single-ended Clocks Device State Latches Open Power Down Low M1 Virtual Power Cycle to Latches Open Hi-Z w/o Latched input w/Latched input CK= Pull down, CK# = Low CK= Pull down CK# = Low CK= Pull down CK# = Low CK= Pull down, CK# = Low CK= Pull down, CK# = Low CK= Pull down CK# = Low Running CK= Pull down, CK# = Low Differential Clocks (Except CPU1) CPU1 CR# 1 0 X Differential Clocks Stoppable Free running Running Running CK= Pull down, CK# = Low CK = Pull down, CK# = Low X Differential Clocks Stoppable Free running Running CK= High CK# = Low CK= Pull down CK# = Low Low Running Running Running
IDTTM/ICSTM PC MAIN CLOCK
1397--11/08/10
12
ICS9LP525-2 PC MAIN CLOCK
General SMBus serial interface information for the ICS9LP525-2 How to Write:
* * * * * * * * Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the beginning byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) starT bit T Slave Address D2(H) WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1 ACK P stoP bit
ACK X Byte Byte N + X - 1 N P Not acknowledge stoP bit
IDTTM/ICSTM PC MAIN CLOCK
1397--11/08/10
13
ICS9LP525-2 PC MAIN CLOCK
Byte 0 FS Readback and PLL Selection Register
Bit 7 6 5 4 3 2 1 Pin Name FSLC FSLB FSLA iAMT_EN Reserved SRC_Main_SEL SATA_SEL Description Type 0 1 Default Latch CPU Freq. Sel. Bit (Most Significant) R See Table 1 : CPU Frequency Select CPU Freq. Sel. Bit Latch R Table CPU Freq. Sel. Bit (Least Significant) Latch R Set via SMBus or dynamically by CK505 if detects RW Legacy Mode iAMT Enabled 0 dynamic M1 Reserved RW 0 Select source for SRC Main Select source for SATA clock RW SRC Main = PLL1 SRC Main = PLL3 Latch RW SATA = SRC_Main SATA = PLL2 0
0
-
PD_Restore
1 = on Power Down de-assert return to last known state 0 = clear all SMBus configurations as if cold powerConfiguration Not RW Saved on and go to latches open state This bit is ignored and treated at '1' if device is in iAMT mode.
Configuration Saved
1
Byte 1 DOT96 Select and PLL3 Quick Config Register
Bit 7 6 5 4 3 2 1 0 Pin 13/14 Name SRC0_SEL PLL1_SSC_SEL PLL3_SSC_SEL PLL3_CF3 PLL3_CF2 PLL3_CF1 PLL3_CF0 PCI_SEL Description Select SRC0 or DOT96 Select 0.5% down or center SSC Select 0.5% down or center SSC PLL3 Quick Config Bit 3 PLL3 Quick Config Bit 2 PLL3 Quick Config Bit 1 PLL3 Quick Config Bit 0 PCI_SEL Type RW RW RW RW RW RW RW RW 0 SRC0 Down spread Down spread 1 DOT96 Center spread Center spread Default 0 Latch 0 0 0 0 1 1
See Table 2: PLL3 Quick Configuration Only applies if Byte 0, bit 2 = 0. PCI from PLL1 PCI from SRC_MAIN
Byte 2 Output Enable Register
Bit 7 6 5 4 3 2 1 0 Pin Name REF_OE USB_OE PCIF5_OE PCI4_OE PCI3_OE PCI2_OE PCI1_OE PCI0_OE Description Output enable for REF, if disabled output is tristated Output enable for USB Output enable for PCI5 Output enable for PCI4 Output enable for PCI3 Output enable for PCI2 Output enable for PCI1 Output enable for PCI0 Type RW RW RW RW RW RW RW RW 0 Output Disabled Output Output Output Output Output Output Output Disabled Disabled Disabled Disabled Disabled Disabled Disabled 1 Output Enabled Output Output Output Output Output Output Output Enabled Enabled Enabled Enabled Enabled Enabled Enabled Default 1 1 1 1 1 1 1 1
Byte 3 Output Enable Register
Bit 7 6 5 4 3 2 1 0 Pin Name Reserved Reserved Reserved SRC8/ITP_OE SRC7_OE SRC6_OE SRC5_OE SRC4_OE Description Reserved Reserved Reserved Output enable for SRC8 or ITP Output enable for SRC7 Output enable for SRC6 Output enable for SRC5 Output enable for SRC4 Type RW RW RW RW RW RW RW RW 0 Disabled Disabled Disabled Disabled Disabled 1 Output Enabled Output Enabled Output Enabled Output Enabled Output Enabled Default 1 1 1 1 1 1 1 1
Output Output Output Output Output
IDTTM/ICSTM PC MAIN CLOCK
1397--11/08/10
14
ICS9LP525-2 PC MAIN CLOCK
Byte 4 Output Enable and Spread Spectrum Disable Register
Bit 7 6 5 4 3 2 1 0 Pin Name SRC3_OE SATA/SRC2_OE SRC1_OE SRC0/DOT96_OE CPU1_OE CPU0_OE PLL1_SSC_ON PLL3_SSC_ON Description Output enable for SRC3 Output enable for SATA/SRC2 Output enable for SRC1 Output enable for SRC0/DOT96 Output enable for CPU1 Output enable for CPU0 Enable PLL1's spread modulation Enable PLL3's spread modulation Type RW RW RW RW RW RW RW RW 0 Output Disabled Output Disabled Output Disabled Output Disabled Output Disabled Output Disabled Spread Disabled Spread Disabled 1 Output Enabled Output Enabled Output Enabled Output Enabled Output Enabled Output Enabled Spread Enabled Spread Enabled Default 1 1 1 1 1 1 1 1
Byte 5 Clock Request Enable/Configuration Register
Bit 7 6 5 4 3 2 1 0 Pin Name CR#_A_EN CR#_A_SEL CR#_B_EN CR#_B_SEL CR#_C_EN CR#_C_SEL CR#_D_EN CR#_D_SEL Description Enable CR#_A (clk req), PCI0_OE must be = 1 for this bit to take effect Sets CR#_A to control either SRC0 or SRC2 Enable CR#_B (clk req) Sets CR#_B -> SRC1 or SRC4 Enable CR#_C (clk req) Sets CR#_C -> SRC0 or SRC2 Enable CR#_D (clk req) Sets CR#_D -> SRC1 or SRC4 Type RW RW RW RW RW RW RW RW 0 Disable CR#_A CR#_A -> SRC0 Disable CR#_B CR#_B -> SRC1 Disable CR#_C CR#_C -> SRC0 Disable CR#_D CR#_D -> SRC1 1 Enable CR#_A CR#_A -> SRC2 Enable CR#_B CR#_B -> SRC4 Enable CR#_C CR#_C -> SRC2 Enable CR#_D CR#_D -> SRC4 Default 0 0 0 0 0 0 0 0
Byte 6 Clock Request Enable/Configuration and Stop Control Register
Bit 7 6 5 4 3 2 1 Pin Name CR#_E_EN CR#_F_EN Reserved Reserved Reserved Reserved SSCD_STP_CRTL (SRC1) SRC_STP_CRTL Description Enable CR#_E (clk req) -> SRC6 Enable CR#_F (clk req) -> SRC8 Reserved Reserved Reserved Reserved If set, SSCD (SRC1) stops with PCI_STOP# Type RW RW RW RW RW RW RW 0 Disable CR#_E Disable CR#_F Free Running 1 Enable CR#_E Enable CR#_F Stops with PCI_STOP# assertion Stops with PCI_STOP# assertion Default 0 0 0 0 0 0 0
0
If set, SRCs (except SRC1) stop with PCI_STOP#
RW
Free Running
0
Byte 7 Vendor ID/ Revision ID
Bit 7 6 5 4 3 2 1 0 Pin Name Rev Code Bit Rev Code Bit Rev Code Bit Rev Code Bit Vendor ID bit Vendor ID bit Vendor ID bit Vendor ID bit Description 3 2 1 0 3 2 1 0 Revision ID Type R R R R R R R R 0 1 Default X X X X 0 0 0 1
Vendor specific
Vendor ID ICS is 0001, binary
IDTTM/ICSTM PC MAIN CLOCK
1397--11/08/10
15
ICS9LP525-2 PC MAIN CLOCK
Byte 8 Device ID and Output Enable Register
Bit 7 6 5 4 3 2 1 0 Pin Name Device_ID3 Device_ID2 Device_ID1 Device_ID0 Reserved Reserved SE1_OE SE2_OE Description Table of Device identifier codes, used for differentiating between CK505 package options, etc. Reserved Reserved Output enable for SE1 Output enable for SE2 Type R R R R RW RW RW RW 0 56-pin device Disabled Disabled Enabled Enabled 1 Default 0 0 0 0 0 0 0 0
Byte 9 Output Control Register
Bit 7 6 5 4 3 2 1 0 Pin Name PCIF5 STOP EN TME_Readback REF Strength Test Mode Select Test Mode Entry IO_VOUT2 IO_VOUT1 IO_VOUT0 Description Allows control of PCIF5 with assertion of PCI_STOP# Truested Mode Enable (TME) strap status Sets the REF output drive strength Allows test select, ignores REF/FSC/TestSel Allows entry into test mode, ignores FSB/TestMode IO Output Voltage Select (Most Significant Bit) IO Output Voltage Select IO Output Voltage Select (Least Significant Bit) Type RW R RW RW RW RW RW RW 1 Default Stops with Free running PCI_STOP# 0 assertion normal operation no overclocking Latch 1X (2Loads) 2X (3 Loads) 1 Outputs HI-Z Outputs = REF/N 0 Normal operation Test mode 0 1 0 1 0
See Table 3: V_IO Selection (Default is 0.8V)
Byte 10 Stop Enable Register
Bit 7 6 5 4 3 2 1 0 Pin Name SRC5_EN Readback Reserved Reserved Reserved Reserved Reserved CPU 1 Stop Enable CPU 0 Stop Enable Description Readback of SRC5 enable latch Type R RW RW RW RW RW RW RW 0 CPU/PCI Stop Enabled Free Running Free Running 1 SRC5 Enabled Stoppable Stoppable Default Latch 0 0 0 0 0 1 1
Reserved
Enables control of CPU1 with CPU_STOP# Enables control of CPU 0 with CPU_STOP#
Byte 11 iAMT Enable Register
Bit 7 6 5 4 3 2 1 0 Pin Name PCI3_CFG1 PCI3_CFG0 Reserved Reserved CPU2_AMT_EN CPU1_AMT_EN PCI-E_GEN2 CPU 2 Stop Enable Description See PCI3 Configuration Table 28 Reserved Reserved Determines if CPU2 runs in M1 mode. Only valid if ITP_EN=1. See Note. Determines if CPU1 runs in M1 mode. See Note. Determines if PCI-E Gen2 compliant Enables control of CPU 0 with CPU_STOP# Type R R RW RW RW RW R RW 0 1 See PCI3 Configuration Table Does not Run Does not Run non-Gen2 Free Running Runs Runs PCI-E Gen2 Compliant Stoppable Default Latch Latch 0 1 0 1 1 1
IDTTM/ICSTM PC MAIN CLOCK
1397--11/08/10
16
ICS9LP525-2 PC MAIN CLOCK
Byte 12 Byte Count Register
Bit 7 6 5 4 3 2 1 0 Pin Name Reserved Reserved BC5 BC4 BC3 BC2 BC1 BC0 Description Type RW RW RW RW RW RW RW RW 0 1 Default 0 0 0 0 1 1 0 1
Read Back byte count register, max bytes = 32
Byte 13 to 28 Reserved Byte 29 Slew Rate Control
Bit 7 6 5 4 3 2 1 Pin Name USB_Slew1 USB_Slew0 PCI_Slew1 PCI_Slew0 Reserved REF Slew Rate Reserved Description USB Slew Rate Control (MSB) USB Slew Rate Control (LSB) PCI Slew Rate Control (MSB) PCI Slew Rate Control (LSB) Changes Ref Slew Rate RW RW RW RW RW RW RW RW 0 1 See Slew Rate Selection Table See Slew Rate Selection Table 1.2V/ns 2.2V/ns Default 1 0 1 1 1 1 0
IDTTM/ICSTM PC MAIN CLOCK
1397--11/08/10
17
ICS9LP525-2 PC MAIN CLOCK
Test Clarification Table
Comments
FSLC/ TEST_SEL HW PIN
HW
SW
REF/N or HI-Z B9b4
FSLB/ TEST TEST_MODE ENTRY BIT HW PIN B9b3
Power-up w/ TEST_SEL = 1 to enter test mode Cycle power to disable test mode FSLC./TEST_SEL -->3-level latched input If power-up w/ V>2.0V then use TEST_SEL If power-up w/ V<2.0V then use FSLC FSLB/TEST_MODE -->low Vth input TEST_MODE is a real time input If TEST_SEL HW pin is 0 during power-up, test mode can be invoked through B9b3. If test mode is invoked by B9b3, only B9b4 is used to select HI-Z or REF/N FSLB/TEST_Mode pin is not used. Cycle power to disable test mode, one shot control
<2.0V >2.0V >2.0V >2.0V
X 0 0 1
0 X X X
0 0 1 0
OUTPUT NORMAL HI-Z REF/N REF/N
>2.0V
1
X
1
REF/N
<2.0V
X
1
0
HI-Z
<2.0V
X
1
1
REF/N
B9b3: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION) B9b4: 1= REF/N, Default = 0 (HI-Z)
IDTTM/ICSTM PC MAIN CLOCK
1397--11/08/10
18
ICS9LP525-2 PC MAIN CLOCK
56-Lead, 300 mil Body, 25 mil, SSOP SYMBOL A A1 b c D E E1 e h L N VARIATIONS N 56 D mm. MIN 18.31 MAX 18.55 MIN .720 D (inch) MAX .730 In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
Ordering Information
9LP525BF-2LFT
Example:
XXXX B F LF T
Designation for tape and reel packaging Lead Free, RoHS Compliant Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 to 7 digit numbers)
IDTTM/ICSTM PC MAIN CLOCK
1397--11/08/10
19
ICS9LP525-2 PC MAIN CLOCK
N
c
L
E1 INDEX AREA
E
12
a
D
A2 A1
A
56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) (20 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 D SEE VARIATIONS SEE VARIATIONS E 8.10 BASIC 0.319 BASIC E1 6.00 6.20 .236 .244 e 0.50 BASIC 0.020 BASIC L 0.45 0.75 .018 .030 N SEE VARIATIONS SEE VARIATIONS 0 8 0 8 aaa -0.10 -.004 VARIATIONS
-Ce
b SEATING PLANE
N 56
10-0039
D mm. MIN MAX 13.90 14.10
D (inch) MIN .547 MAX .555
Reference Doc.: JEDEC Publicat ion 95, M O-153
aaa C
Ordering Information
9LP525BG-2LFT
Example:
XXXX B G LF T
Designation for tape and reel packaging Lead Free, RoHS Compliant Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 to 7 digit numbers)
IDTTM/ICSTM PC MAIN CLOCK
1397--11/08/10
20
ICS9LP525-2 PC MAIN CLOCK
Revision History
Rev. A B Issue Date Description 6/23/2008 Going to Release 1. Updated Pin Description 8/8/2008 2. Added Byte 29 for Slew Rate control Page # 2-3, 17
C D E F
1) Byte 11, bit 5 is now reserved. 2) Byte 29, bits 7:6 default to 0.8X slew rate (`10') 3) Removed reference to STOP drive mode in Power management table. 4) Corrected REF slew rate control from Byte 29b3 to Byte 29b2. 5) Clarified description of Byte 11, bits 2 and 3 to reflect CK505 ME clock selection table. Various 10/10/2008 6) Marked as Reserved all bits that are not in the 56-pin version of the device 10, 11, 1) updated tables 2, 6 and 7 to clarify interaction of Config Modes with SRC1 19, 20 4/28/2009 2) Updated ordering revision to A. 4/30/2009 Updated ordering revision. 19,20 11/8/2010 Removed last time buy statement 1
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015 408-284-8200 Fax: 408-284-2775
For Tech Support
408-284-6578 pcclockhelp@idt.com
Corporate Headquarters
Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.)
Asia Pacific and Japan
Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505
Europe
IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339
TM
(c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA
21

▲Up To Search▲

Price & Availability of ICS9LP525-2

	To Download ICS9LP525-2 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .